The goal of 3D XPoint is to break the memory (SRAM, DRAM) or storage (NAND SSD, HDD) barrier by offering an in-between solution. Even though the technology is fairly new, the research does indicate better system performance. Where the technology distinguishes itself is with its low latency of ~10 μs which 100 times slower than DRAM but 1000 times faster than NAND SSD. This means the system remains responsive even under load because the CPU isn’t wasting time waiting for the memory and so, CPU performance is increased. Furthermore, 3D XPoint offers better endurance and long term reliability due to its nature. The technology can be rewritten up to 20,000 cycles before degrading as opposed to 1,000-3,000 for traditional NAND SSD. This last technology holds data by storing electrical charges in cells, but it will slowly leak energy if left for long periods without power, which results in data loss. Therefore, they are not suited for archival storage. 3D XPoint gets its name from its architecture of a stackable cross-gridded data access array. Submicroscopic columns of selectors and memory cells are meshed at the intersection of perpendicular wires. Each cell can be addressed individually by sending a current through the corresponding top and bottom wires. This design allows for several layers to be stacked in three dimensions to improve the scalability and it is reported by Intel to have a storage density up to 8 to 10 times greater than DRAM. The 3D XPoint technology is based on phase-change materials (PCM). The technology has an unspecified composition,. These metalloids have the physical properties of holding multiple stable states with distinctive resistance characteristic. Each cell’s selector verifies a change operation and applies the appropriate voltage to the material to change its atomic structure between an amorphous insulator and a crystalline conductor. Each resistance level represents a value of 0 or 1 and will hold its values indefinitely. Therefore, it isn’t affected by power loss because it doesn’t use silicon to form energy dependant transistors like DRAM. Furthermore, there is no “erase” action required to program a PCM cell because it can be set regardless of its previous state, unlike NAND flash and data must be erased before new data can be written.